Semiconductor devices typically include a plurality of layers of circuit patterns formed on top of a substrate. During the process for manufacturing such semiconductor devices, in order to accurately align the plurality of layers of circuit patterns with one another, alignment marks used for positioning or alignment are formed in mark formation regions in a prescribed layer of the substrate. When the substrate is a semiconductor wafer (hereinafter, simply referred to as “wafer”), these alignment marks are also known as wafer marks.
The smallest (finest) circuit patterns in conventional semiconductor devices are formed using a dry lithography or liquid immersion lithography process performed using a dry or immersion-type (liquid immersion-type) exposure device having an exposure wavelength of 193 nm, for example. It has been predicted that formation of circuit patterns smaller (finer) than the 22 nm node, for example, will be difficult even when using conventional optical lithography in combination with the double patterning process being developed more recently.
Recently, methods for forming circuit patterns smaller than the resolution limits of current lithography technologies by producing nanoscale fine structures (sub-lithographic structures) using directed self-assembly of block copolymers within patterns formed using a lithography process have been proposed (see US Patent Application Laid-open No. 2010/0297847 and Japanese Unexamined Patent Application Publication No. 2010-269304A, for example). Patterned block copolymer structures are also known as microdomains (microphase separation domains) or simply as domains.